Multiprocessor Debug
As more processing elements, features, and functions are simultaneously embedded into the silicon, the emerging level of embedded complexity outstrips the capability of a stand-alone logic analyzer, a debugger, and an emulator-based diagnostic tool.
While these tools allow the capture of data off the system data bus, they work only as long as every access (read or write) occurs over the external data bus. For embedded processors and buses with no direct external access, this points to a growing gap in effectively being able to provide the necessary controllability and, in particular, the
visibility of the internal operations of a complex system.
The need for improved methods of observing and analyzing embedded proces- sor and SoC operation has increased at a pace at least proportional to the explosive growth in SoC designs and new IP cores. This forces the analysis side of the SoC world into a constant process of catching-up to the designer’s ability to add cores and integrate new resources on chip. With an ever-shortening development cycle, and often several generations of products being produced in parallel or rapid suc- cession, standardized embedded tools and capabilities that enable quick analysis
and debug of the embedded IP are a critical factor in keeping SoC verification a manageable part of the process.
Before we can implement an on-chip debug system suitable for multicore systems
we have to ask the user requirements.
1. Each core and bus must be observable. We must be able to see or reconstruct the
program flow of each single core independently as well as of the data flow on the system buses. Also important are signals allowing conclusions to be drawn about power modes, bus accessing modes, and others.
2. It is crucial for system analysis to recognize events that arise from interactions between the cores and buses. A single core on its own is no longer of interest. Rather, events coming from several cores have to be considered. To minimize this challenge, cross triggers must be used, which combine events from different sources and make them available systemwide.
3. The interactions between all SoC components during debug become more com- plex as more components are involved. A debug system with complex cross triggering is hard for the user to manage. The debugger as a user interface for the complex debug hardware must support the user in its work finding the mistakes or performance bottlenecks. It has to hide the complexity that comes with multicore debugging. We must not forget the user’s task is to cope not with the debug hardware itself but with the faulty system.
On-chip instruments (and simulation) play an important part of SoC development and verification flows, providing the ability to analyze what is happening on the hardware itself, during both prototyping and system-level verification stages, and increasingly on the final products themselves. The problem in analyzing informa- tion like embedded buses in hardware in many cases hinges on a problem of visibility: it is difficult to fix what you cannot see. This visibility problem for the embedded SoC is more complex than can be addressed adequately by traditional on-chip test methods such as traditional JTAG scan, for several reasons:
Bus operations are multicycle, with signals in a bus cycle becoming active at – different times, requiring sequential tracing rather than as a single-cycle snap- shot that scans typically provide. Bus operation problems are interrelated with the operations of at least two com- – municating blocks (a processor and memory peripheral, for example). Traditional debug methods, such as halting part of a system for testing, can introduce changes and new variables that interfere with the test scenario and process. If problems are intermittent or sparse, then trace operations need to operate in a – triggered mode, so information for a given range of bus cycles of interest is captured in real time.
The problem is, to a large extent, a multicore extension of embedded processor analysis, with run control, instruction execution, and data trace as integral parts of processor support. For larger systems with multiple cores, the problem extends beyond processor execution to understanding system operation and communica- tions (Fig. 2.9).
In formal terms, multicore embedded systems present an asymmetric functional test problem. Their controllability is high, because the systems are dominated by programmable processor cores. The observability is low, however, in terms of both the critical signals that are directly available and the amount of embedded logic and internal signals as a ratio of the available IO in which to observe them. Adding dedicated resources and structures that support functional analysis is necessary to increase system observability. This requires a hierarchical focus to the issue of system analysis, starting at the individual core level of debug instrumentation and resources and increasing to a more system-centric diagnostic capability to facilitate increased observability. While embedded debug instrumentation approaches are becoming increasingly common at the core level, system-level diagnostics and analysis at the multicore level have historically been a largely underaddressed area in complex embedded systems.
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